This invention relates to circuits for receiving a clock signal and generating multiple buffered duplications of the received clock signal such that any skew between the duplicated signals is minimal. Such a circuit is herein called a clock deskew circuit.
A primary use of the clock deskew circuit is in a multi-chip clocked logic system. In such a system, a clocked flip-flop "A" which is located on one chip often has an output which goes to an input of a clocked flip-flop "B" which is located on another chip. If the edge of the clock signals which trigger those two flip-flops do not occur at precisely the same time, a race condition can occur which will cause logic errors. For example, if flip-flop "A" is clocked early while flip-flop "B" is clocked late, the input to flip-flop "B" might change just as that flip-flop is being clocked.
To provide clock signals for the flip-flops on all of the chips which are precisely synchronized to each other is not an easy task. In particular, a single clock signal cannot simply be sent to each of the chips and there duplicated as many times as needed by multiple clock buffers. That is because the time delay through a clock buffer will unavoidably vary from one chip to another; and that variance in time delay will produce a skew between the buffered clock signals. Differences in time delay through the buffers are unavoidable because they are caused by many minute process variations which occur as the chips are fabricated.
In the prior art, the problem of dealing with clock skew is addressed in U.S. Pat. No. 4,637,018. However, the clock deskew circuit of that patent can only deskew the buffered clock signals in certain predetermined increments. For example, if a clock edge occurs too late, it is sped up by a certain fixed increment of time. But, depending on how late the clock edge was to begin with, that fixed increment of time may be too large. Further, since the minimal size of this fixed increment is limited, the degree to which it affects clock skew increases as the cycle time of the clock decreases. Consequently, for very high speed clocked logic systems, this patent has little or no value.
Also in the prior art, the clock deskew problem is addressed in U.S. Pat. No. 4,494,021. In this patent, the skew between buffered clock signals on different chips is reduced in a continuous fashion through the use of a voltage-controlled oscillator (VCO) which operates in conjunction with the variable delay line. However, with a VCO, the clock signal cannot be stopped since a VCO has an internal feedback loop which causes it to always oscillate. Being able to stop the clock is, however, a useful feature for various purposes--such as for doing maintenance on the clocked logic system and for putting the clocked logic system in a temporary wait state until some needed response from another external source is received.
Further, the amount of circuitry that is required to implement the '021 clock deskew circuit is quite large since the VCO circuitry is essentially doubled by the delay line circuitry. Also with patent '021, the delay line lies external to the VCO feedback loop, and thus the time delay through the delay line is not self-calibrating. Instead, the delay through the delay line is set by the operation of the VCO and by making the delay line stages identical to the VCO stages. However, in a mass production environment, the delay line stages and the VCO stages cannot always be exactly alike due to unavoidable processing variations, impedance loading variations, and mask variations.
Accordingly, the primary object of the invention is to provide an improved clock deskew circuit in which all of the above described problems are eliminated.